RISC-V
This section describes how to develop projects including RISC-V processors
Welcome to the RISC-V section of Deploying with Sabana.
With Sabana you can deploy hardware images that contain RISC-V CPUs into the cloud. This section will guide you through the details of every step of the process, from source code to interacting with a deployed instance:
- Creating a new image
- Compiling C code for the CPU
- Creating a test program
- Testing the image
Although this section is focused on RISC-V you can apply the same process to package any CPU into an image
Overall the process of creating a new image with a RISC-V CPU can be summarized as follows:
- Create a new project
- Choose the interfaces required by the CPU
- Integrate the CPU into the new project
- Push the project to Sabana for it to be built into an image
In our examples we have used a customized Ez shell with a RAM to integrate the RISC-V CPU. Interacting with the image requires the following steps:
- Write any inputs to a predefined memory location in the CPU's RAM
- Write the C program to be executed at the start of the CPU's RAM
- Start the processing
- Wait for the processing to finish
- Read out the outputs from a predefined memory location in the CPU's RAM
By taking a look at the following sections you will:
- Learn how to use the Sabana compilation service of C programs to create the binaries that will run on your CPU.
- Learn how to create a Sabana shell to quickly integrate your RISC-V or other CPUs.
Let's get stared!
Last modified 3mo ago